A shift register that shift the bits 1 position to the right at each clock pulse is initialized to 1100(Q0, Q1, Q2., Q3 ). The outputs are combined using an XOR gate circuit and fed to the D input. After which clock pulse, will the initial pattern reappear at the output? (A) 6 th (B) 5 th (C) 4 th (D) 7 th | Numerade
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