IEEE

Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors

Abstract: The use of Large Language Models (LLMs) in hardware design has taken off in recent years, principally through its incorporation in tools that increase chip designer productivity. There has ...
IEEE

A New IEEE Milestone: Development of the BELLMAC-32 Microprocessors, 1976–1982 [A New IEEE Milestone]

Abstract: On 17 February 2025, the IEEE Board of Directors designated the BELLMAC-32 development as a historic milestone. Commemorative plaques will be placed on the walls of Nokia Bell Labs, Murray ...
IEEE

An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC–DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS

Abstract: This article presents an energy-efficient microprocessor design that fully integrates an error-resilient RISC-V core and an embedded dc–dc switched-capacitor voltage regulator (SCVR). The ...
IEEE

Quantum Computing Simulation on VLIW Microprocessors

Abstract: This paper presents the development of a quantum computing simulator on the Elbrus VLIW microprocessor architecture. The simulator is designed to efficiently simulate quantum algorithms by ...
IEEE

Microprocessor Design Space Exploration via Space Partitioning and Bayesian Optimization

Abstract: Design space exploration (DSE) has long been a very important topic in electronic design automation (EDA), but the growing diversity of applications and the complexity of integrated circuits ...
IEEE

Design and Implementation of a Low Power Arithmetic and Logic Unit for MIPS32 Processor

Abstract: Today's technology is around designing low power electronic devices. Thus, to address the challenge, this paper introduces a novel clock gating approach targeting the arithmetic and logic ...
IEEE

IBM Telum II Microprocessor: 5.5 GHz With On-Die AI and Data Processing, and Design–Technology Co-Optimizations for Power, Area, and Reliability

Abstract: The IBM Telum II microprocessor features eight cores operating at a base frequency of 5.5 GHz, ten 36-MB L2 caches achieving 3.6-ns access latency, a 360-MB virtual L3 cache, and a new ...
kiowacountypress.net

Growing microprocessors instead of wheat in northeast Colorado?

A data center that may soon be formally proposed in northeastern Colorado shocks me in its potential demand for electricity. A behemoth. The data center may require up to two gigawatts of electricity, ...
arkvalleyvoice

Growing Microprocessors Instead of Wheat?

Logan County wants economic development. Might this sparsely settled area of northeastern Colorado become home to a hyperscale data center? A data center that may soon be formally proposed in ...
IEEE

Distributed Self-Interleaving PWM Signals With Fault-Tolerant Capability for High-Performance Microprocessor Power Supply in Aerospace

Abstract: In this article, we introduce a novel distributed self-interleaving management solution with enhanced noise immunity for multiphase converters applications. This solution, in conjunction ...
IEEE

Microprocessor Instruction Design Tool for RISC-V Architecture

Abstract: We have been developing MEIMAT (MEiji Microprocessor Architecture Design Tools). The MEIMAT is essentially designed to be able to represent any instruction of various processors by the ...
IEEE

A Master-Slave Distributed Power Management Architecture for Dynamic Voltage and Frequency Scaling (DVFS) for Low Power Microprocessor

Abstract: This paper presents an effective master-slave distributed voltage and frequency modulation circuit for processors in system-on-chip (SoC). This work achieves dynamic voltage and frequency ...