Semiconductor Engineering

Fine-Grained Functional Partitioning For Low Level SRAM Cache in 3D-IC designs (imec)

A new technical paper titled “Towards Fine-grained Partitioning of Low-level SRAM Caches for Emerging 3D-IC Designs” was published by researchers at imec. “We propose a partitioning of low-level ...
Design-Reuse

SiliconBlue iCE65 mobileFPGA Family Strengthens Consumer Handheld Leadership with World's First Wafer Level Chip Scale Package SRAM FPGAs

Leading-edge technology for smallest board space and maximum FPGA logic & I/Os In production now at 0.4mm & sampling 0.5mm ball pitch die-sized WLCSPs Leadership technology co-developed and ...