If you read Japanese, you might have seen the book “Design and Implementation of Microkernels” by [Seiya Nuda]. An appendix covers how to write your own operating system for RISC-V in about 1,000 ...

IAR Embedded Workbench is a commercial embedded development toolchain, known for powerful code optimisation and a reliable ...

Last month, a team of Google security researchers released a tool that can modify microcode of AMD's processors based on the Zen microarchitecture, the Zentool. While this is a security vulnerability, ...

The state of RISC-V, including new RISC-V announcements. A look at some good video presentations at the 2024 RISC-V Summit. RISC-V trends in 2025. I didn't make it to the RISC-V Summit this year.

RISC-V, pronounced “risk five,” is a modern open-source instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. In simple terms, it’s like a blueprint that ...

The Android ecosystem is hurtling toward a RISC-V future. The puzzle pieces for the up-and-coming CPU architecture started falling into place this past year when Google announced official RISC-V ...

RISC-V architecture is an open, international standard governing how software interfaces with hardware in a computer. It serves as a shared language that sets the parameters for communication and ...