EDN

Flash and Logic Process Integration

Spansion Inc. and United Microelectronics Corporation announced the joint development of a 40nm process that integrates UMC’s 40nm LP logic process with Spansion® proprietary embedded Charge Trap (eCT ...
Electronic Design

Could This “2D” Transistor Process Transform Logic and Power Device Production?

CDimension’s technology, which enables semiconductor makers to manufacture arrays of extremely small, fast, and efficient “2D” transistors, has the potential to change what’s possible for both digital ...
Design-Reuse

Virage Logic First to Deliver Complete Memory Compiler and Logic Library IP Portfolio for TSMC 40nm Process

SiWare Physical IP Provides Built-in Power Management Capabilities to Meet Tight Power Budgets FREMONT, Calif.-- April 07, 2008 --Virage Logic Corporation, the semiconductor industry’s trusted IP ...
EDN

Logic 101 – Part 2 – Positive vs Negative Logic

1. Logical versus arithmetic views of a digital function. Having said this, it is generally preferable to employ a single consistent format to cover both cases, and it is easier to view logical ...