Electronic Design

Eye-Diagram Analysis Speeds DDR SDRAM Validation

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...
EDN

DDR3 memory interface controller IP speeds data processing applications

DDR3 memory systems can provide a significant performance boost to a variety of data processing applications. However, compared to previous generations (DDR and DDR2), DDR3 memory devices have some ...
Design-Reuse

Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions

Choosing the right type of memory is critical to ensure that the power and performance requirements are met for the target application. Memory technologies have significantly evolved over the last ...
Electronic Design

Leverage High-Frequency Source-Synchronous Memory in SoC Design

Download this article in PDF format. Today’s embedded systems require high external memory bandwidth to achieve fast boot time and application loading time with minimal cost. Historically, ...
EDN

Implementing an all-digital PHY and delay-locked loop for high-speed DDR2/3 memory interfaces

A high-speed DDR2, DDR2/3, or DDR3 DRAM interface for off-chip memory provides a powerful tool to meet the high-performance demands of new electronic products. However, with advancements come new ...