Semiconductor Engineering

Logic Synthesis Basics For FPGA

In the early days of digital design, all circuits were designed manually. You would draw K-map, optimize the logic and draw the schematics. If you remember, we all ...
EDN

Mentor’s first wave of new FPGA synthesis tools targets 50 million gate designs

WILSONVILLE, Ore. — Three months after disclosing an ambitious plan to redefine design software for field programmable gate arrays, Mentor Graphics Corp. here is preparing to ship its first beta ...
Semiconductor Engineering

HW Security: Flip-Flops Along Logic Gates to Prevent Synthesis Tools’ Structural Leakages (TU Dresden, Ruhr Univ. Bochum)

A new technical paper titled “Flip-Lock: A Flip-Flop-Based Logic Locking Technique for Thwarting ML-based and Algorithmic Structural Attacks” was published by researchers at TU Dresden and Ruhr ...
EDN

Product Update: FPGA and PLD Design Tools

The ACTgen Macro Builder is a parameterized macro function generator that enables users to construct highly efficient counters, adders, and other structured blocks. Developed as a productivity and ...